Random access memory (“RAM”) devices are used as storage devices in various applications such as computer systems, mobile phones, and video systems. Dynamic RAMs (DRAMs) and static RAMs (SRAMs) are two such RAM devices. Both DRAMs and SRAMs include memory cells arranged in rows and columns to form an array. In operation, information in the memory cells is typically accessed during an “access cycle”.
Memory cells in a DRAM include a capacitor and a transistor and are thus relatively small in size. Data can be stored in the DRAM cell by charging the capacitor. The capacitor, however, gradually discharges over time, and must be periodically recharged or refreshed. During a refresh cycle, an entire row of DRAM cell capacitors are typically recharged. Through a series of such cycles, the entire DRAM array is refreshed.
Each memory cell in an SRAM cell generally constitutes a flip-flop circuit, often including as many as six transistors. Although information in an SRAM memory cell can be accessed faster than in a DRAM cell, SRAMs typically consume more power and lack the storage density achievable with DRAMs.
A pseudo-SRAM cell is known that combines advantages of both DRAM and SRAM cells. Pseudo SRAM cells include a capacitor, but the refresh operation is “hidden” or “concealed”. Exemplary Pseudo-SRAMs are described in U.S. Pat. No. 4,549,284 to Ikuzaki, entitled “Dynamic MOS Random Access Memory,” U.S. Pat. No. 6,028,804 to Leung, entitled “Method and Apparatus for 1-T SRAM Compatible Memory,” and U.S. Pat. No. 6,625,077 to Chen, entitled “Asynchronous Hidden Refresh of Semiconductor Memory”, each of which is incorporated by reference herein.
Conventional pseudo-SRAM cells may be refreshed either by a pipeline operation or a scheduled operation. In a pipeline operation, a refresh cycle is performed prior to an access cycle, which may disadvantageously result in higher power consumption. In a scheduled operation, lower power consumption or reduced access cycle time can be achieved, but may require a more complex refresh circuit including, for example, an external refresh circuit. There is thus a need for a memory device having simpler circuitry and improved power consumption.